The present invention relates to semiconductor devices, and more particularly to semiconductor devices that are fabricated on a silicon-on-insulator (SOI) substrate wherein the devices contain an active well region formed therein.
To obtain optimal tradeoffs between high drive current Idsat and low off current Ioff, device and circuit designers are looking at various approaches including active wells. In an active well design, the standby current can be kept low by raising the field effect transistor (FET) threshold voltage Vt, hence reducing the sub-threshold leakage current. The threshold voltage level is adjusted by biasing the isolated well containing the FET. During an active cycle, the well is biased to lower the Vt for high switching speeds.
There are several ways of making active wells work in bulk complementary metal oxide semiconductor (CMOS) technology. The simplest way is to implement a triple-well process in which both NFET and PFET bodies are contained in isolated wells. This prior art bulk process requires an extra masking step and extra penalizing layout rules. Moreover, this prior art approach has high well capacitance, which is a challenge to bias quickly with low power.
Insofar as silicon-on-insulator (SOI) technology is concerned, there is no easy way to implement an active well process in such technology. One method of making low-resistance body contacts using a wafer bonding technique is described, for example, in S. Kuehne, et al. xe2x80x9cSOI MOSFET with Buried Body Strap by Wafer Bondingxe2x80x9d, IEEE Trans. Electron Devices, Vol. 45, pp. 1084-1091, May 1998.
A typical SOI NFET structure is shown, for example, in FIG. 1A. Specifically, the SOI NFET of FIG. 1A comprises buried oxide layer 12 sandwiched between Si-containing substrate 10 and top Si-containing layer 14. Note that top Si-containing layer is the layer of the SOI substrate in which active devices will be formed. As shown, top Si-containing layer includes isolation regions 16, n+ diffusion regions 18 and p-body region 20. The prior art SOI NFET also contains gate dielectric 22 and gate stack 24 formed atop the top Si-containing layer as well as spacers 26 that are formed on the exposed vertical sidewalls of at least gate stack 24. In such a structure, the p-body is highly resistive and is not easily shared among many devices.
A bulk CMOS device design, which is complementary to the SOI design shown in FIG. 1A, is shown in FIG. 1B. Specifically, the device design shown in FIG. 1B comprises p substrate 50 having p-body 52, shallow trench isolation regions 54 and n+ diffusion regions 56 formed therein. Atop of substrate 50 is the gate of the device, which comprises gate dielectric 58, gate stack 60 and sidewall spacers 62. The structure shown in FIG. 1B has lower junction capacitance and may provide tighter well layout rules than a conventional bulk CMOS structure. Despite these advantages, however, the bulk CMOS structure shown in FIG. 1B suffers from having high well capacitance, thus making the SOI structure of FIG. 1A more desirable.
It is noted that SOI technology is becoming increasingly important since it permits the formation of high-speed circuits. Moreover, SOI devices offer many more advantages over their bulk counterparts including, higher performance, absence of latch-up, higher packing density and low voltage applications. In view of the advantages of SOI devices over bulk CMOS devices, there is a need for developing an active well process for SOI technology that can be easily implemented and that will afford the above advantages of active wells in SOI devices.
One object of the present invention is to provide a semiconductor device that is fabricated on an SOI substrate wherein the device contains an active well region therein.
Another object of the present invention is to provide a semiconductor device that is fabricated on an SOI substrate wherein control of the well potential is achieved without the need of using metallic contacts.
A further object of the present invention is to provide a semiconductor device that is fabricated on an SOI substrate wherein optimal tradeoffs between high drive current Idsat and low off current Ioff are achieved.
A yet further object of the present invention is to provide a semiconductor device that is fabricated on an SOI substrate in which the body of the device has a low resistance and can be easily shared among many devices.
These and other objects and advantages are achieved by adding a buried interconnect plane to a structure between the top Si-containing layer and the buried oxide layer of an SOI substrate. The buried interconnect plane employed in the present invention is either p+ for an NFET or n+ doped for a PFET. Due to the low-resistance of the interconnect plane, many FETs can share the same well region.
One aspect of the present invention relates to a semiconductor device which is fabricated on an SOI substrate. Specifically, the semiconductor device of the present invention comprises:
a field effect transistor structure comprising at least a body and diffusion regions;
a buried interconnect plane contacting the body and, optionally self-aligned to the diffusion regions;
an isolation oxide region between the diffusion regions and the buried interconnect plane; and
a buried oxide layer present beneath said buried interconnect plane, said buried oxide layer present atop a Si-containing substrate.
In the semiconductor device of the present invention, the diffusion regions, the body of the FET and the buried interconnect plane form a non-rectifying electrically conductive path.
More specifically, the semiconductor device of the present invention comprises:
a field effect transistor structure comprising a gate stack, a gate dielectric, source/drain diffusions, sidewall spacers, and a body;
a buried interconnect plane on a first surface of a buried oxide layer opposing a second surface of said buried oxide layer in contact with a Si-containing substrate, the buried interconnect plane contacting the body of said field effect transistor and, optionally self-aligned to the source/drain diffusions;
an isolation oxide region adjacent to said body, the isolation oxide region being between said source/drain diffusions and the buried interconnect plane.
Another aspect of the present invention relates to various methods for forming the above-mentioned SOI device which includes an active well region formed therein. One method of the present invention relates to a non-self-aligned method of fabricating the inventive structure.
Specifically, the non-self-aligned method includes the steps of:
(a) forming a silicon-on-insulator substrate (SOI) substrate, said SOI substrate having a patterned top Si-containing layer present atop a buried oxide region which includes areas that are exposed;
(b) forming a mask over a portion of said patterned top Si-containing layer;
(c) forming regions of porous Si in portions of said patterned top Si-containing layer not protected by said mask;
(d) removing the mask and the regions of porous Si from said patterned top Si-containing layer so as to provide a cavity in said regions previously occupied by porous Si;
(e) forming an isolation oxide region within said cavity; and
(f) forming a field effect transistor on a portion of said patterned top Si-containing layer, wherein said field effect transistor includes at least diffusion regions formed within said top Si-containing layer above said isolation oxide region, said diffusion regions being separated by a body region.
Note a deep implant region, which forms the interconnect plane of the inventive device, can be formed immediately after step (c) or after step (f).
In another embodiment of the present invention, a self-aligned method of forming the inventive SOI structure containing active well formed therein is provided. In the self-aligned method, the method of the present invention comprises the steps of:
(a) forming an SOI substrate comprising at least a buried oxide region having a patterned top Si-containing layer formed on a portion of said buried oxide region;
(b) forming a patterned gate level on a portion of said patterned top Si-containing layer, said patterned gate level including at least a hardmask formed atop a gate material;
(c) forming sidewall spacers on portions of said patterned gate level;
(d) forming porous Si regions within said patterned top Si-containing layer;
(e) removing said hardmask and said porous Si regions;
(f) forming an oxide within said removed porous Si regions and forming an oxide layer over said buried oxide region, said patterned top Si-containing layer, said sidewall spacers and said gate material; and
(g) etching back portions on said oxide layer so as to expose at least a portion of said patterned top Si-containing layer abutting said patterned gate level, while leaving oxide in at least said removed porous silicon regions.
Note a deep implant region, which forms the interconnect plane of the inventive device, can be formed after step (d).